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FS8160 1.1 GHz/1.1 GHz Dual Phase-locked Loop IC
HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior notice. HiMARK Technology, Inc. assumes no responsibility for the use of any circuits shown in this datasheet.
Description
The FS8160 is a serial data input, fully programmable dual phase-locked loop IC for use in the local oscillator subsystem of radio transceivers. When combined with external VCOs, the FS8160 becomes the core of a very low power dual frequency synthesizer wellsuited for mobile communication applications. The FS8160 is pin-compatible with National Semiconductor's LMX1602 IC.
Features
Supply voltage operating range: 2.7 to 3.6 V Maximum input frequency: 1.1 GHz/1.1 GHz (main/auxiliary) Low current consumption (IDD,total typically 5 mA at VDD,main = VDD,aux = 3.0 V and < 1 A in power down mode) 16-bit programmable input (both main and auxiliary) frequency dividers (including a / 16/17 prescaler) with divide ratio range from 240 to 65535 12-bit programmable reference (both main and auxiliary) frequency dividers with divide ratio range from 2 to 4095 Programmable charge pump output Digital-filtered lock detect output 16 pin, plastic TSSOP (0.65 mm pitch)
Package and Pin Assignment
16 pin, plastic TSSOP (dimensions in mm)
FOLD XIN XOUT VSSA FINA VDDA DOA ENA
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
CLK DATA LE VSSM FINM VDDM DOM ENM
HiMARK
FS8160
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FS8160
Pin Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name FOLD XIN XOUT VSSA FINA VDDA DOA ENA ENM DOM VDDM FINM VSSM LE DATA CLK I/O O I O -- I -- O I I O -- I -- I I I Description Multiplexed CMOS level output (see Programming Description section) Reference crystal oscillator or external clock input with internally biased amplifier Reference crystal oscillator output used with external resonator Ground (aux PLL) VCO frequency input with internally biased input amplifier (aux PLL) Nominal 3.0 V supply voltage (aux PLL) Single-ended charge pump output (aux PLL) Enable control input; normal operation when high, power-down mode when low (aux PLL) Enable control input; normal operation when high, power-down mode when low (main PLL) Single-ended charge pump output (main PLL) Nominal 3.0 V supply voltage (main PLL) VCO frequency input with internally biased input amplifier (main PLL) Ground (main PLL) Latch enable input Serial data input Shift register clock input
Functional Block Diagram
FINM XIN XOUT DATA CLK LE ENM ENA
MAIN PRESCALER
N-COUNTER PFD R-COUNTER MAIN LATCH
LOCK DETECTOR FOLD MUX LOCK DETECTOR CHARGE PUMP
DOM
OSC
CONTROL LOGIC
SHIFT REGISTER
FOLD
AUX LATCH R-COUNTER
FINA
AUX PRESCALER
PFD N-COUNTER
CHARGE PUMP
DOA
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FS8160
Absolute Maximum Ratings
VSS = 0 V
Parameter Supply voltage Symbol VDD,main VDD,aux VFIN,main VFIN,aux TOPR TSTG TSLD tSLD Rating VSS - 0.3 to VSS + 6.5 VSS - 0.3 to VSS + 6.5 VSS - 0.3 to VDD,main + 0.3 VSS - 0.3 to VDD,aux + 0.3 -40 to 85 -40 to 125 255 10 Unit V V V V C C C s
Input voltage range Operating temperature range Storage temperature range Soldering temperature range Soldering time range
Recommended Operating Conditions
VSS = 0 V
Value Parameter Symbol min. VDD,main Supply voltage range VDD,aux Operating temperature TA VDD,main -40 25 VDD,main 85 V C 2.7 typ. max. 3.6 V Unit
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Electrical Characteristics
(VDD,main = VDD,aux = VDD = 3.0 V, TA = 25 C unless otherwise noted)
Value Parameter Symbol Condition min. GENERAL Current consumption Standby current consumption FIN operating frequency range IDD,total IDD,standby fFIN 1.1 GHz + 1.1 GHz 1.1 GHz only ENM = ENA = low Main Auxiliary Logic mode Crystal mode Main Auxiliary 100 100 1 1 -15 -15 0.5 5.0 2.5 1 1100 1100 40 20 0 0
VDD,aux
Unit typ. max.
mA mA A MHz MHz MHz MHz dBm dBm Vpk-pk
XIN operating frequency range
fXIN
FIN input sensitivity XIN input sensitivity DIGITAL INTERFACE Logic LOW input voltage Logic HIGH input voltage Logic LOW input current Logic HIGH input current XIN logic LOW input current XIN logic HIGH input current
PFIN VXIN
VIL VIH IIL IIH IIL,XIN IIH,XIN VIL = 0 V, VDD = 3.6 V VIH = VDD = 3.6 V VIL = 0 V, VDD = 3.6 V VIH = VDD = 3.6 V Logic mode, VXOUT = VDD/2, VDD = 3.6 V Crystal mode, VXOUT = VDD/2, VDD = 2.7 V IOL = 500 A IOH = -500 A VDD - 0.4 |300| 0.8 x VDD -1 -1 -100
0.2 x VDD
V V
1 1
A A A
100 |200|
A A A
XOUT output current magnitude
IXOUT
Logic LOW output voltage Logic HIGH output voltage SERIAL PROGRAMMING TIMING DATA to CLK setup time DATA to CLK hold time
VOL VOH
0.4
V V
tSU1 tH1
50 10
nS nS
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FS8160
Electrical Characteristics (continued)
(VDD,main = VDD,aux = VDD = 3.0 V, TA = 25 C unless otherwise noted)
Value Parameter Symbol Condition min. CLK to LE setup time CLK pulse width logic HIGH CLK pulse width logic LOW LE pulse width CHARGE PUMP High gain mode, VDOM,VDOA = VDD/2 Low gain mode, VDOM,VDOA = VDD/2 High gain mode, VDOM,VDOA = VDD/2 Low gain mode, VDOM,VDOA = VDD/2
0.5 V V DOM ,VDOA V DD - 0.5 V
Unit typ. max. nS nS nS nS
tSU2 tPWH tPWL tPW
50 50 50 50
-1600
A A A A nA
IDO,source Charge pump output current IDO,sink
-160
+1600
+160 1
Charge pump high-Z state current
IDO,high-Z
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FS8160
Functional Description
The FS8160 dual phase-locked loop (PLL) IC contains two identical PLLs (main and auxiliary). Both the main and auxiliary PLLs share the crystal oscillator, serial data input logic, and multi-function lock detector output circuits. Each PLL has its own programmable input and reference frequency dividers, phase/frequency detectors, programmable charge pumps, and digital-filtered lock detectors. Programmable Input Frequency Divider The VCO input to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as fV. The programmable input frequency divider consists of a / 16/17 (P/P+1) dual-modulus prescaler and a 16-bit (N) counter, which is further comprised of a 4-bit swallow (A) counter, and a 12-bit main (B) counter. The total divide ratio, M, is related to values for P, A, and B through the relation
M = ( P + 1 ) x A + P x ( B - A ) = P x B + A,
with B A. The minimum programmable divisor for continuous counting is given by P x ( P - 1 ) = 16 x 15 = 240, and the valid total divide ratio range for the input divider isM = 240 to 65535. Programmable Reference Frequency Divider The crystal oscillator output is divided by the programmable divider and then internally output to the PFD as fR. The programmable reference frequency divider consists of a 13bit reference (R) counter. Because of its design, the valid total divide ratio range for the reference divider is R = 2 to 4095.
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Phase/Frequency Detector (PFD) The PFD compares an internal input frequency divider output signal, fV, with an internal reference frequency divider output signal, fR, and generates an error signal which is proportional to the phase error between fV and fR. The polarity of the PFD is user-selectable using serial input data control bits (see Table 5 on page 9). The input/output waveforms for a positive polarity PFD (VCO frequency increases with increasing tuning voltage) are shown in Fig. 1. Fig. 1 - Positive polarity PFD input/output waveforms
fR fV high-Z DOM, DOA high-Z high-Z
Charge Pump The charge pump output sources/sinks current to/from an external loop filter, which converts the charge into a voltage used to control the external VCO's frequency. When the PLL is locked, the charge pump output is primarily in a high impedance (high-Z) state. The magnitude of the charge pump output current is user-selectable using serial input data control bits (see Table 5 on page 9). Serial Input Data Format The divide ratios for the input (N) and reference (R) dividers are input using an 18-bit serial interface consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The format of the serial data is shown in Fig. 2. Fig. 2 - Serial input data format
MSB LSB DATA[15:0] 17 21 CB[1:0] 0 Page 7
The data on the DATA line is written to the shift register on the rising edge of the CLK signal and is input with MSB first. The data on the DATA line should be changed on the falling edge of CLK, and LE should be held low while data is being written to the shift register. Data is transferred from the shift register to one of the four (4) frequency divider latches when LE is set high depending upon the state of the control bits (CB[1:0]) as indi-
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FS8160
cated below. Table 1: Latch enable control bits
CB[1]
0 0 1 1
CB[0]
0 1 0 1
Latch Location
Aux. R Aux. N Main R Main N
The definition of the contents of the shift register relating to each particular latch location is listed in the table below. Table 2: Serial data input format
First bit 17 Aux. R Aux. N Main R Main N CP_CNTRL[3:0] MAINB[11:0] 16 15 14 13 12 11 Shift Register Bit Location 10 9 8 7 6 5 4 3 2 1 0 AUXA[3:0] MAINR[11:0] MAINA[3:0] 0 1 1 Last bit 0 0 1 0 1
FOLD[3:0] AUXB[11:0]
AUXR[11:0])
The 12-bit main and auxiliary reference (R) divider ratios are specified by the MAINR[11:0] and AUXR[11:0] bits, respectively, and are defined in the table below. Table 3: Reference divider ratios
Divide Ratio 2 3 MAINR[11:0] and AUXR[11:0] 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 1 1 0 0 1
*
4095
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
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FS8160
Similarly, the 16-bit main and auxiliary input (N) divider ratios are specified by the MAINA[3:0] + MAINB[11:0] and AUXA[3:0] + AUXB[11:0] bits, respectively, and are defined in the table below. Table 4: Input divider ratios
Divide Ratio 11 3 4 0 0 10 0 0 9 0 0 MAINB[11:0] and AUXB[11:0] 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 1 1 1 0 0 1 0 0 1 Divide Ratio MAINA[3:0] and AUXA[3:0] 3 0 0 2 0 0 1 0 0 0 0 1
*
4095
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
15
*
1
*
1
*
1
*
1
The charge pump control bits CP_CNTRL[3:0] set (1) the phase detector polarity and (2) the magnitude of the charge pump source/sink current, and are defined below. Table 5: Charge pump and PFD control bits
Bit
CP_CNTRL[3] CP_CNTRL[2] CP_CNTRL[1] CP_CNTRL[0]
Latch Location
Main R, bit 17 Main R, bit 16 Main R, bit 15 Main R, bit 14
Function
Aux. charge pump current Main charge pump current Aux. phase/frequency detector polaritya Main phase/frequency detector polarity
"0"
Low, 160 A Low, 160 A Negative Negative
"1"
High, 1600 A High, 1600 A Positive Positive
a. When the VCO frequency increases with increasing control voltage, set the phase/frequency detector polarity to positive. When the VCO frequency decreases with increasing control voltage, set the phase/frequency detector polarity to negative.
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The outputs selected by the FOLD[3:0] control bits for the multiplexed FOLD output pin are defined in the table below. Table 6: Multiplexed FOLD output control bits
FOLD[3]
Aux. R, bit 17 0 0 0 0 0 1 1 1 1
FOLD[2]
Aux. R, bit 16 0 0 0 1 1 0 0 1 1
FOLD[1]
Aux. R, bit 15 0 0 1 0 1 0 1 0 1
FOLD[0] FOLD Output State
Aux. R, bit 14 0 1 x x x x x x x "0" "1" Main lock detector output Aux. lock detector output Main AND Aux. lock detector output Main R-divider output Aux. R-divider output Main N-divider output Aux. N-divider output
Serial input data timing waveforms are shown in Fig. 3. Fig. 3 - Serial input data timing waveforms
DATA
tSU1 tPWH tPWL tSU2
tH1
CLK LE
tPW
MSB
DATA
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
CLK
LE
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LSB
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FS8160
Lock Detector The lock detector incorporates a filter which compares the phase error between the inputs to the PFD to an R-C generated delay of 15 ns. To enter the locked state (output is high), the phase error must be less than 15 ns for four (4) consecutive cycles. Once in the locked state, the generated R-C delay is changed to 30 ns. To exit the locked state (i.e. lock detector output goes low), the phase error must become greater than the 30 ns delay. When the PLL is in stand-by mode, the lock detector output is forced low. A flow chart representing the operation of the lock detector is given below.
Start Un-locked state (output LOW) Phase error < 15 ns Yes Phase error < 15 ns Yes Phase error < 15 ns Yes Phase error < 15 ns Yes Locked state (output HIGH) No Phase error > 30 ns Yes No
No
No
No
Crystal Oscillator The internal crystal oscillator circuitry may be used in either of two modes: crystal mode -- with an external crystal resonator (crystal mode) or logic mode -- with an external reference frequency source such as a TCXO (logic mode). The FOLD[3:0] control bits select
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the operation mode of the crystal oscillator according to the table below. Table 7: Crystal oscillator mode control bits
FOLD[3]
Aux. R, bit 17 0 0
FOLD[2]
Aux. R, bit 16 0 0
FOLD[1]
Aux. R, bit 15 0 0
FOLD[0] Crystal Oscillator Mode
Aux. R, bit 14 0 1 Crystal mode Crystal mode Logic mode Crystal mode
All other states
A typical crystal oscillator circuit implementing a 10 MHz oscillator in crystal mode is given in the figure below. Fig. 4 - 10 MHz crystal oscillator circuit
OSC
2 XIN
3 XOUT 18
30 pF
30 pF
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FS8160
Application Circuit
FOLD
30 pF 10 MHz 30 pF 1nF 18 K
FOLD XIN
CLK DATA
FS8160 HIMARK
XOUT VSSA
LE VSSM FINM VDDM DOM ENM
18 100 pF 1 nF
from C VCO
VCO
100 pF
FINA VDDA DOA ENA
18
VCC
100 pF 1 F 1 F 100 pF
VCC
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April 2003

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